Dr. Mayank Shrivastava
Assistant Professor
Department of Electronic Systems Engineering
Indian Institute of Science Bangalore, 560012
E-mail: mayank@dese.iisc.ernet.in 
Contact: +91-80-2293-2732
Age: 31
mayank-border

Biography

Prof. Mayank Shrivastava's research interest broadly covers nanoelectronics / nano-technological solutions for system on chip and system on board applications. Other than this he also works on high voltage / high power devices for system on chip / power electronic applications and on-chip ESD reliability. He has taken several positions within the semiconductor industry. During 2008 and again in 2010, he was a Visiting Scholar at Infineon Technologies AG, Munich, Germany. During 2010-2011, he worked for Infineon Technologies, East Fishkill, NY, USA and later Intel, Mobile & Communications Group, Hopewell Junction, NY, USA. From Oct. 2011 till Aug. 2013 he was with Intel, Mobile & Communications Group, Munich Germany. Since September 2013 he is with DESE at IISc Bangalore.

Prof. Shrivastava has over 50 publications in international journals/conferences, has 21 United States patents and 5 Indian patents issued or pending in his field of interest. He is selected as the recipient of the prestigious IEEE EDS Early Career Award for year 2015. He was a recipient of the India TR35 award for the year 2010 (Young Innovator Award from MIT Technology Review 35); 2008 Best Research Paper Award in circuit design category from Intel Corporation Asia Academic Forum; the 2008 Industrial Impact Award from IIT Bombay; the biography publication by the International Biographical Center, Cambridge, U.K., in the 2000 Outstanding Intellectuals of the 21st Century in 2010; the Excellence in Thesis work for his Ph.D. thesis from IIT Bombay and Infineon PhD fellowship for 3 years.

Area of Research

VLSI

o  Nanoelectronics

o  Solid State Physics

o  Semiconductor device design, modeling, processing and characterization

o  Power Semiconductors

Research Interest

Graphene, Carbon Nanotubes and novel 1D/2D materials

o  Nanoscale device design and modeling

o  Beyond CMOS

o  Light Weight and Flexible High Performance Electronics

o  Device-circuit co-design

o  Electrothermal modeling

o  On-chip ESD Protection

o  Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT)

o  LDMOS and DeMOS HV/Power device design

o  Nanotechnology for Mobile Systems

Analog Memory for Neuromorphic applications

Key Contributions

Prof. Shrivastava has over 50 international publications and 27 patents. His one of the key contributions has been enablement and integration of nanoscale CMOS and drain extended MOS devices in advanced CMOS nodes for future System on Chip (SoC) applications. His innovations on FinFETs, integrated high voltage switching and RF devices, as well as electrostatic discharge protection (ESD) devices for advanced CMOS technologies has enabled the semiconductor industries in the design and manufacturing of SoC in advanced nano-scale CMOS nodes including FinFETs.

Open Positions:

I don't offer undergraduate internship positions. Students interested in fundamental or applied research and looking for research positions can contact me directly with their research interest and CV. Prospective PhD students should also look for the IISc admission procedure while contacting me.  

Work Experience

1.   Assistant Professor, Department of Electronic Systems Engineering, Indian Institute of Science Bangalore (September 2013 - Present).

2.   Staff Engineer: Intel Corp. (MCG), Munich, Germany (April. 2013 - August 2013).

Senior Engineer: Intel Corp. (MCG), Munich, Germany (Sep. 2011 - March 2013).

Responsible for:

o  28nm ESD protection concepts and library development.

o  14nm ESD device and technology co-development, ESD device characterization, simulation and modeling topics.

3.   Senior Engineer: Infineon Technologies, USA (Sep 2010 to Jan 2011) and Intel Corp. (MCG), USA, (Feb 2011 to Sep 2011).

Responsible for:

o  28nm & 20nm ESD device and technology co-development, ESD device characterization, simulation and modeling topics at the IBM facilities in Essex Junction, VT and Hopewell Junction, NY, USA under the International Semiconductor Development Alliance.

4.   Visiting Scholar: Infineon Technologies, Munich, Germany. April 2008 to Oct 2008 and again from May 2010 to July 2010.

Details of Professional Recognitions, Awards, and Fellowships received:

1.   2015 IEEE EDS Early Career Award, one of the highest honours given by IEEE Electron Device Society (EDS). (Presented at the International Electron Device Meeting, Washington DC, USA)

2.   India TR35, 2010, Young Innovator Award. Technology Review's TR35 list by Massachusetts Institute of Technology recognizes the outstanding innovators under the age of 35 each year. Received on March 8, 2010

3.   Award for Excellence in Thesis Work, IIT Bombay-2010, received on 6th August, at the 48th convocation of IIT Bombay.

4.   IIT Bombay - Industrial Impact Award, for pursuing research work that caused maximum industry impact. Received on September 6, 2010 by Dr. N. Mukunda, who is a prominent Indian theoretical physicist.

5.   Best Research paper Award, Intel Asia Academic Forum 2008, Oct 2008, Taipei, Taiwan.

6.   2000 Outstanding Intellectuals of the 21st Century-2010 - Biography publication by International Biographical Center (IBC), Cambridge, England

7.   Infineon Fellowship, Duration: November 2008- July 2010

8.   Technical Program Committee (TPC)

o  EOSESD symposium 2012, 2013, 2014 (Session/Sub-com chair), 2015, 2016

o  IWPSD 2015 (Sub-com Chair)

o  IEEE VLSI Design 2011, 2014, 2015 (Vice-chair, "Device and Process Technology" session)

o  IEEE ESSDERC 2014 - 2016

9.   Reviewer for several journalsincluding JJAP, MR, IEEE T-ED, IEEE EDL and IEEE TDMR

o  Listed 6 times (2009, 2010, 2012 - 2015) in the IEEE T-ED golden list of reviewers

o  Listed 4 times (2012, 2013 - 2015) in the IEEE EDL golden list of reviewers

10.                   Editor for Electronic Devices and Components of IETE Journal of Research

Publicity / Press Coverage

Rajya Sabha TV: https://youtu.be/k9u2Ji9Vlbk?list=PLVOgwA_DiGzpd3_Iz7J-81Vh4QqU-ZGA9
Technology Review: http://www2.technologyreview.com/tr35/profile.aspx?TRID=860
DNA: http://www.dnaindia.com/india/report-iit-b-makes-it-to-mit-s-top-innovators-list-1361475
Deccan Herald: http://www.deccanherald.com/content/58465/beyond-classroom.html
Indian Express: http://www.indianexpress.com/news/towards-smaller-better-gadgets/587650/0
NDTV: http://www.ndtv.com/news/sci-tech/iit_infineon_achieve_breakthrough_for_system-on-chip.php
EE Herald: http://www.eeherald.com/section/news/nw10000592.html
EE Times: http://www.eetimes.com/author.asp?section_id=36&doc_id=1284049
EE Times: http://www.eetimes.com/electronics-news/4083184/Infineon-Indian-researchers-claim-ESD-advance
Rediff: http://business.rediff.com/report/2009/apr/22/iit-achieves-breakthrough.htm
Bangalore Mirror: http://www.bangaloremirror.com/bangalore/others/New-transistor-design-is-a-breakthrough/articleshow/49897633.cms
Indian Express: http://indianexpress.com/article/technology/technology-others/from-the-lab-a-new-device-for-more-efficient-phones-computers/
IISc Press: http://iisc.researchmedia.center/article/iisc-researcher%E2%80%99s-new-transistor-design-%E2%80%93-breakthrough-chip-technology
Indian Express: http://www.newindianexpress.com/cities/bengaluru/IISc-Prof-Wins-Major-Global-Award/2015/10/29/article3102225.ece
Deccan Herald: http://www.deccanherald.com/content/515146/bengaluru-scientist-wins-coveted-ieee.html
Hindu: http://www.thehindu.com/news/cities/bangalore/honour-for-iisc-professor/article7816056.ece
Global Indians: http://www.globalindian.indiaincorporated.com/iisc-prof-wins-major-global-award/
IEEE: http://eds.ieee.org/early-career-award.html
IISc Press:: http://iisc.researchmedia.center/article/iisc-professor-wins-major-international-award
Deccan Herald: http://www.deccanherald.com/content/509822/iisc-faculty-devises-technology-shrink.html

Talks

Courses Offered:

1.   Reliability of Nanoscale Circuits and Systems

2.   Advanced ESD devices, circuits and design methods

3.   Power Semiconductor Devices and Physics

 

Students:

1.         Adil Meersha (PhD)

2.         Abhishek Mishra (PhD)

3.         Milova Paul (PhD)

4.         Harsha B (PhD)

5.         Sampath B (PhD)

6.         Kranthi N. S. (PhD)

7.         Ankit Soni (PhD)

8.         Hemanjaneyulu Kuruva (PhD)

9.         Bhawani Shankar (PhD)

10.     Satyajith B (PhD)

11.     Ansh (PhD)

12.     Rajat Sinha (PhD)

13.     Kaushik (ME)

 

List of Patents

Granted/Issued (United States Patent Office):

  1. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei," Semiconductor devices with trench isolations", United States Patent (2012) 8,097,930
  2. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, "Operational Amplifier Having Improved Slew Rate " United States Patent (2012) 8,089,314
  3. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, "Nonvolatile floating gate analog memory cell", United States Patent (2013) 8,436,413
  4. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, "Field-effect device and manufacturing method thereof", United States Patent (2013) 8,354,710
  5. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, Ramgopal Rao, Christian Russ, "Device and method for coupling first and second device portions", United States Patent (2013) 8,455,947
  6. 6. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, "Drain extended field effect transistors and methods of formation thereof", United States Patent (2013) 8,536,648
  7. Mayank Shrivastavaand Harald Gossner, "Drain extended MOS device for Bulk FinFET technology", United States Patent (2014) 8,629,420
  8. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, "Semiconductor devices and methods for manufacturing a semiconductor device", United States Patent (2014) 8,643,090
  9. Mayank Shrivastava, Christian Russ, Harald Gossner, "Low voltage ESD clamping using high voltage devices", United States Patent (2014) 8,654,491
  10. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, Ramgopal Rao, "High voltage semiconductor devices", United States Patent (2014) 8,664,720
  11. Mayank Shrivastava, Christian Russ, Harald Gossner, "Selective current pumping to enhance low-voltage ESD clamping using high voltage devices", United States Patent (2014) 8,681,461
  12. Mayank Shrivastavaand Harald Gossner, "Silicon controlled rectifier (SCR) device for bulk FinFET technology", United States Patent (2015) 8,785,968
  13. Mayank Shrivastava, Christian Russ and Harald Gossner, "Tunable Fin-SCR for Robust ESD Protection", United States Patent (2015) 8,963,201
  14. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, "Field-Effect Device and Manufacturing Method Thereof", United States Patent 9,035,375
  15. Mayank Shrivastava, Christian Russ, Harald Gossner, V. Ramgopal Rao, "Drain Extended Field Effect Transistors and Methods of Formation Thereof", United States Patent: 9,087,892

Published/Patent Pending (United States Patent Office):

  1. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, "Methods for manufacturing a semiconductor device", United States Patent 20140113423.
  2. Mayank Shrivastava, Maryam Shojaei Baghini, Christian Russ, Harald Gossner, V. Ramgopal Rao, "High Voltage Semiconductor Devices", United States Patent 20140145265
  3. Mayank Shrivastavaand Christian Russ, "FinFET and Fin-BJT SCR as ESD clamp with Built-In trigger circuit and Current Ballasting mechanism including Checker-Board Layout Technique for Uniform SCR Turn-On", United States Patent 20150008476.
  4. Mayank Shrivastava, Harald Gossner, V. Ramgopal Rao, M. Shojaei, "Field-Effect Device and Manufacturing Method Thereof", United States Patent 20150255450
  5. Mayank Shrivastava, Christian Russ and Harald Gossner, "Tunable FIN-SCR for Robust ESD Protection", United States Patent 20150144997
  6. Christian Russ, Mayank Shrivastava and Markus Schwiegershausen, "Transient-Triggered SCR for FinFET Technology (FF-TTSCR) for ESD Protection of RF IO", United States Patent pending (Filed August 2015).


Filed (Indian Patent Office):
  1. Mayank Shrivastavaand Kuruva Hemanjaneyulu "Fin enabled area scaled tunnel field Effect transistor", Patent Application No: 2625/CHE/2015, Filed on May 26th 2015.
  2. Mayank Shrivastava, "Miniaturized, High Power Density Power Electronic System on a Chip", Patent Application No: 1355/CHE/2015, Filed on March 19th 2015.
  3. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, "Independently Driven Double Gate (IDDG) Nonvolatile floating gate analog memory cell", Indian Patent pending, 2008, Patent Application No 2217/MUM/2008, Filed on 15th October 2008.
  4. Rajesh Thakkar, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, " A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs", Patent Application No 542/MUM/2010, Filed on 2nd March 2010.
  5. Mayank Shrivastava, "Drain extended Tunnel FET", Patent Application No: 201641006497, Filed on Feb 26th 2016.

List of Publications

Publications in IEEE Journals: 26

Publications in the International Electron Devices Meeting (IEDM) & the International Reliability Physics Symposium (IRPS) (the two most prestigious conferences for Electron Devices): 10

 

Books and Book chapters

  1. Chapter titled "Towards Drain extended FinFETs for SoC applications" in book "Towards Quantum FinFET", edited by Weihua Han and Zhiming M. Wang, Springer, Dec 2013.

Journals

  1. Mayur Ghatge and Mayank Shrivastava, "Physical Insights On the Ambiguous Metal Graphene Interface and Proposal for Improved Contact Resistance", IEEE Transactions on Electron Devices, Vol:62, Issue:11, Nov. 2015
  2. Kuruva Hemanjaneyulu and Mayank Shrivastava, "Fin Enabled Area Scaled Tunnel FET", IEEE Transactions on Electron Devices, Vol:62, Issue:10, Oct. 2015
  3. Peeyusha S. Swain, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, "On the Geometrically Dependent Quasi-Saturation and gm Reduction in Advanced DeMOS Transistors", to appear in IEEE Transactions on Electron Devices
  4. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, Harald Gossner, and V. Ramgopal Rao, "On the Improved High-Frequency Linearity of Drain Extended MOS Devices", to appear in IEEE Microwave and Wireless Components Letters
  5. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, "Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain Extended PMOS Device", to appear in IEEE Transactions on Electron Devices
  6. Ketankumar H. Tailor, Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, and V. Ramgopal Rao, "Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device", to appear in IEEE Transactions on Electron Devices
  7. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, "Part II: A Fully Integrated RF PA in 28nm CMOS with Device Design for Optimized Performance and ESD Robustness", IEEE Transactions on Electron Devices, Vol:62, Issue:10, Oct. 2015
  8. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, "Part I: High Voltage MOS Device Design for Improved Static and RF Performance", IEEE Transactions on Electron Devices, Vol:62, Issue:10, Oct. 2015
  9. Mayank Shrivastava, Neha Kulshrestha and Harald Gossner, "ESD Investigations of Multiwalled Carbon Nanotubes", IEEE Transactions on Device and Material Reliability, Nov. 2013.
  10. Peeyush Swain, Mayank Shrivastava, Harald Gossner, M. S. Baghini and V. Ramgopal Rao, "Device-Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors", IEEE Transactions on Electron Devices, Vol. 60, Issue: 11, pp:3827-3834, Nov. 2013. 
  11. Anukool Rajoriya, Mayank Shrivastava, Harald Gossner, Thomas Schulz and V. Ramgopal Rao "Sub 0.5V Operation of Performance Driven Mobile Systems Based on Area Scaled Tunnel FET Devices", IEEE Transactions on Electron Devices, August 2013, Volume: 60, Issue: 8, pp: 2626-2633.
  12. Mayank Shrivastava and Harald Gossner, "A Review on the ESD Reliability of Drain Extended MOS Devices", IEEE Transactions on Device and Material Reliability, Vol. 12, Issue 4, Dec 2012, pp: 615-625. (Invited Review Paper)
  13. Mayank Shrivastava, Harald Gossner and V. Ramgopal Rao, "A Novel Drain Extended FinFET Device for High Voltage High Speed Applications", IEEE Electron Device Letters, Vol. 33, Issue: 10, Oct. 2012, pp: 1432-1434.
  14. Mayank Shrivastava, Harald Gossner and Christian Russ, "A Novel Drain Extended NMOS Device with Spreading Filament under ESD Stress", IEEE Electron Device Letters, Vol. 33, Issue: 9, Sep 2012, pp: 1294-1296
  15. Mayank Shrivastava, Manish Agrawal, Sunny Mahajan, Harald Gossner, Thomas Schulz, Dinesh Kumar Sharma, and V. Ramgopal Rao, "Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures", IEEE Transactions on Electron Devices, May 2012, Volume: 59, Issue: 5.
  16. Mayank Shrivastava, Ruchit Mehta, Shashank Gupta, M. Shojaei Baghini, D. K. Sharma, Harald Gossner, T. Schulz, K. Arnim, W. Molzer, V. Ramgopal Rao, "Towards System On Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines", IEEE Transactions on Electron Devices, June 2011, Volume: 58, Issue: 6 (This paper was recognized as a feature article in the Synopsys newsletter, May 2011).
  17. Ram Asra, Mayank Shrivastava, K. V. R. M. Murali, R. K. Pandey, Harald Gossner and V. Ramgopal Rao, "A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance", IEEE Transactions on Electron Devices, July 2011, Volume: 58, Issue: 7, Pages: 1855-1863. 
  18. Rajesh A. Thakker, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, and Mahesh B. Patil, " A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs", Microelectronics Journals, Volume 42, Issue 5 , May 2011, Pages 758-765.
  19. Mayank Shrivastava, Ruchil Jain, M. Shojaei Baghini, Harald Gossner and V. Ramgopal Rao, "Solution towards the OFF state degradation in Drain extended MOS device", IEEE Transactions on Electron Devices, Dec. 2010, Volume: 57, Issue: 12 .
  20. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, "Insight into the Turn-On Behavior of the Parasitic Bipolar During ESD Stress in Nanometer Scale Drain Extended NMOS Device", IEEE Transactions on Electron Devices, Feb 2011, Volume: 58, Issue: 2.
  21. Amitabh Chatterjee, Mayank Shrivastava, Harald Gossner, Sameer Pendharkar, Forrest Brewer, Charvaka Duvvury, " An Insight into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DENMOS) Devices:2D Study- Biasing & Comparison with NMOS ", IEEE Transactions on Electron Devices, Feb 2011, Volume: 58, Issue: 2
  22. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, "Part I: On the low current parasitic bipolar and base push-out behavior of STI type DeNMOS device under ESD Conditions ", IEEE Transactions on Electron Devices, Sep 2010, Sep 2010, Volume: 57, Issue: 9 .
  23. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, "Part II: On the 3D filamentation and failure modeling of STI type DENMOS Device under ESD Conditions", IEEE Transactions on Electron Devices, Sep 2010, Volume: 57, Issue: 9 .
  24. Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, "A novel bottom spacer FinFET structure for improved power-delay & short channel performance", IEEE Transactions on Electron Devices, June 2010, Volume: 57, Issue: 6 .
  25. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, "PART I-"Mixed Signal Performance of Various High Voltage Drain Extended MOS devices" IEEE Transactions on Electron Devices, Jan 2010, Volume: 57, Issue: 2 .
  26. Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, "PART II-"A Novel scheme to optimize the mixed signal performance and hot carrier reliability of Drain Extended MOS devices" IEEE Transactions on Electron Devices, Jan 2010, Volume: 57, Issue: 2 .
  27. Mayank Shrivastava, Maryam Shojaei Baghini, A. Sachid, Dinesh Kumar Sharma, V. Ramgopal Rao, "A Novel and Robust Approach for Common Mode Feedback using IDDG FinFET", IEEE Transactions on Electron Devices, Nov 2008, Volume: 55, Issue: 11, pp: 3274-3281.

Conferences

  1. Abhishek Mishra and Mayank Shrivastava, "New Insights on the ESD Behavior and Failure Mechanism of Multi Wall CNTs", to appear in the proceedings of IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17-19 April, 2016
  2. Bhawani Shankar and Mayank Shrivastava, "Unique ESD Behavior and Failure Modes of AlGaN/GaN HEMTs", to appear in the proceedings of IEEE International Reliability Physics Symposium, Pasadena, CA, USA, 17-19 April, 2016
  3. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, "Drain Extended MOS Device Design for Integrated RF PA in 28nm CMOS with Excellent FoM and ESD Robustness", IEEE International Electron Device Meeting (IEDM) Dec. 2014, San Francisco, CA, USA.
  4. Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Dinesh Kumar Sharma, A. N. Chandorkar, Harald Gossner and V. Ramgopal Rao, "A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package", IEEE VLSI 2016
  5. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, "On the Breakdown Physics of Trench-Gate Drain Extended NMOS", Electron Devices and Solid-State Circuits Conference, Singapore, June 2015
  6. Ketankumar Tailor, Mayank Shrivastava, Harald Gossner, Maryam Baghini, Ramgopal Rao, "Comparison of Breakdown Characteristics of DeNMOS Devices with Various Drain Structures", Electron Devices and Solid-State Circuits Conference, Singapore, June 2015
  7. Mayank Shrivastava and Harald Gossner, "ESD Behavior of Metallic Carbon Nanotubes", to appear in the proceedings of 36th EOSESD Symposium, 7-12 Sep. 2014, Tucson, Arizona, USA.
  8. Mayank Shrivastava, Christian Russ, Harald Gossner, S. Bychikhin, D. Pogany and E. Gornik, "ESD Robust DeMOS Devices in Advanced CMOS Technologies", 33 rd EOSESD symposium, 11-15 Sep. 2011, Anaheim, California, USA.
  9. Junjun Li, Rahul Mishra, Mayank Shrivastava, Yang Yang, Robert Gauthier, Christian Russ, "Technology Scaling Effects of Silicide-blocked PMOSFET Devices under ESD like conditions in Advanced Nanometer Node Bulk CMOS Technologies", EOSESD symposium, 11-15 Sep. 2011, Anaheim, California, USA.
  10. Mayank Shrivastava, Christian Russ, Harald Gossner, "On the Impact of ESD Implant and Filament Spreading in Drain extended NMOS devices", International ESD Workshop, May 2011, Lake Tahoe, CA, USA.
  11. Mayank Shrivastava, Manish Agrawal, Jasmin Aghassi, Harald Gossner, Wolfgang Molzer, Thomas Schulz, V. Ramgopal Rao, "On the thermal failure in nanoscale devices: Insight towards Heat Transport and Design Guidelines for Robust Thermal Management & EOS/ESD Reliability", IEEE International Reliability Physics Symposium, 10-14 April, 2011, Monterey, CA, USA, pp: 3F.3.1 - 3F.3.5.
  12. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, "On the Transient Behavior of Various Drain Extended MOS Devices under the ESD stress conditions", 7th International SoC Design Conference (ISOCC 2010), November 22-23, Songdo Convensia, Incheon, Korea (Invited)
  13. Saurabh Nema, Mayank Shrivastava, Angada B. Sachid, A. K. Saxena, Anand Bulusu, "A Novel Scaling Strategy for Underlap FinFETs", ICCCD 2010
  14. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini and V. Ramgopal Rao, "3D TCAD based approach for the Evaluation of Nanoscale Devices during ESD Failure", 7th International SoC Design Conference (ISOCC 2010), November 22-23, Songdo Convensia, Incheon, Korea (Invited)
  15.  Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, "On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions", IEEE International Reliability Physics Symposium (IRPS), Anaheim, California, USA, May 2-6, 2010.
  16. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, "On the differences between 3D filamentation and failure of n & p type drain extended MOS devices under ESD condition", IEEE International Reliability Physics Symposium (IRPS), Anaheim, California, USA, May 2-6, 2010.
  17. Mayank Shrivastava, Harald Gossner, Maryam Shojaei Baghini, V. Ramgopal Rao, "Reliability aware I/O design for sub 45nm node CMOS technology", IWPSD-2009, 15th -19 th Dec, 2009 (Invited).
  18. Mayank Shrivastava, Bhaskar Verma, M. Shojaei Baghini, Christian Russ, Dinesh K. Sharma, Harald Gossner, V. Ramgopal Rao, "Benchmarking the Device Performance at sub 22 nm node Technologies using an SoC Framework", IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009.
  19. Mayank Shrivastava, S. Bychikhin, D. Pogany, Jens Schneider, M. Shojaei Baghini, Harald Gossner, Erich Gornik, V. Ramgopal Rao, "Filament Study of STI type Drain extended NMOS device using Transient Interferometric Mapping", IEEE International Electron Device Meeting (IEDM), 7th -9th Dec, 2009.
  20. Mayank Shrivastava, Jens Schneider, Ruchil Jain, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, "IGBT plugged in SCR device for ESD protection in advanced CMOS technology", EOS/ESD symposium, August 30 - September 4, 2009, Anaheim, CA, USA.
  21. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, "Highly resistive body STI: n-DEMOS: An optimized DEMOS device to achieve moving current filaments for robust ESD protection", IEEE International Reliability Physics Symposium (IRPS), April 26 - 30, 2009, Montreal, Quebec, Canada.
  22. Mayank Shrivastava, Jens Schneider, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao, "A New Physical Insight and 3D Device Modeling of STI Type DENMOS Device Failure under ESD Conditions", IEEE International Reliability Physics Symposium (IRPS), April 26 - 30, 2009, Montreal, Quebec, Canada.
  23. A. B. Sachid, Mayank Shrivastava, R. A. Thakkar, M. Shojaei Baghini, D. K. Sharma, M. B. Patil, V. Ramgopal Rao, "Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies", Intel Asia Academic Forum 2008, 20-22 Oct 2008, Taipei, Taiwan (received the best research paper award).

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